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D-type latches
Octal Transparent D-Type Latches With 3-State Outputs
Data sheet
- document-pdfAcrobat SNx4HCT373 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G) PDF | HTML
SN74HCT373
Product details
- Operating voltage range of 4.5 V to 5.5 V
- High-current 3-state true outputs can drive up to 15 LSTTL loads
- Low power consumption, 80-µA max ICC
- Typical tpd =21 ns
- ±6-mA output drive at 5 V
- Low input current of 1 µA max
- Inputs are TTL-voltage compatible
- Eight high-current latches in a single package
- Full parallel access for loading
- Operating voltage range of 4.5 V to 5.5 V
- High-current 3-state true outputs can drive up to 15 LSTTL loads
- Low power consumption, 80-µA max ICC
- Typical tpd =21 ns
- ±6-mA output drive at 5 V
- Low input current of 1 µA max
- Inputs are TTL-voltage compatible
- Eight high-current latches in a single package
- Full parallel access for loading
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Technical documentation
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View all 13Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | SNx4HCT373 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G) | PDF | HTML | 13 Jul 2022 |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 Dec 2022 | |
Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
User guide | Signal Switch Data Book (Rev. A) | 14 Nov 2003 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 Jun 1997 | ||
Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
Application note | SN54/74HCT CMOS Logic Family Applications and Restrictions | 01 May 1996 | ||
Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 Apr 1996 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages
The 14-24-LOGIC-EVM evaluation module(EVM)is designed to support any logic device that is in a 14-pin to 24-pinD, DW, DB, NS, PW, DYYor DGV package,
User guide: PDF | HTML
Not available on TI.com
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
PDIP (N) | 20 | Ultra Librarian |
SOIC (DW) | 20 | Ultra Librarian |
SOP (NS) | 20 | Ultra Librarian |
TSSOP (PW) | 20 | Ultra Librarian |
TI's Standard Terms and Conditions for Evaluation Items apply.
Ordering & quality
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Learn more
Information included:
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- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
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Information included:
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